Posted by: Anonymous
[ip: 70.144.46.105]
on September 09, 2008 05:54 AM
Wrong other Anonymous, Now with AMD CPU's, the FSB doesn't leave the CPU for the traditional memory controler on a distant northbridge. No mo chipset-influenced
(B)i(t)CH memory timing/compatibility issues. And íntel is still stuck producing a matching pair of bridge chips for EVERY intel CPU, a sales model which they are just now re-evaluating.
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Long Live the FSB
Posted by: Anonymous [ip: 70.144.46.105] on September 09, 2008 05:54 AM(B)i(t)CH memory timing/compatibility issues. And íntel is still stuck producing a matching pair of bridge chips for EVERY intel CPU, a sales model which they are just now re-evaluating.
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