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Intel’s Future Haswell Processor to Feature Transactional Synchronization

Intel’s James Reinders writes that the company will be introducing new Transactional Synchronization Extensions (TSX) for the future 22 nm multicore processor code-named “Haswell”. In a nutshell, Intel TSX provides a set of instruction set extensions that allow programmers to specify regions of code for transactional synchronization. With transactional synchronization,...

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Marc Hamilton on HPC Design Challenges

HP’s Marc Hamilton came away from a recent meeting on future HPC Design Challenges with some interesting thoughts on power, cooling, and IO. Flash roadmaps are well understood and seeing evolutionary improvements. However, the looming mainstream introduction of PCIeGen3 server interconnects and new PCIeGen3 flash controllers offers interesting possibilities.

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Fujitsu Launches Cloud Services as a Platform for Big Data

Today Fujitsu launched something called Data Utilization Platform Services, which use cloud services as a platform for leveraging big data. This is a cloud service for gathering, compiling, and integrating massive quantities of sensing data, processing it using realtime processing or batch processing, and using it for such purposes as...

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Cyprus Unveils Largest Supercomputer in Eastern Mediterranean

This week the largest supercomputer in the Eastern Mediterranean was unveiled at the Cyprus Institute’s Computation-based Science and Technology Research Centre (CaSToRC). The IBM system is a hybrid CPU/GPU cluster currently holding 1,392 processors, each with 48 GB memory in 116 nodes.

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Podcast: Interview with Dr. Bernd Mohr on the ISC’s Popular Crash Course on HPC

In this podcast, I interview Dr. Bernd Mohr from the Jülich Supercomputer Center. Every year at the ISC International Supercomputing Conference in Germany, Dr. Mohr conducts a popular half-day Crash Course on High Performance Computing to help familiarize conference attendees with all the terminology we bat around here in supercomputing circles.

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