How to disable the I-cache of only CPU1?
Hello, I was working for one of the usecase where the requirement was to disable the I-cache of CPU1 only.This use case was needed for SetTop Box development which uses Cortex-A9 Dual core (where CPU0 is master core and CPU1 is secondary core) I tried following steps to do disable the I-cache of CPU1: 1. Set "CONFIG_CPU_ICACHE_DISABLE" using menuconfig option. 2. Inside arch/arm/kernel/head.S file modified following code: #ifdef CONFIG_CPU_ICACHE_DISABLE - bic r0, r0, #CR_I + mrc p15, 0, r5, c0, c0,5 + ands r5, r5, #0xFF + bicne r0, r0, #CR_I @ Disable core1 Icache #endif This is to Disable I-cache for CPU1 (CPU0 I-cache is already enabled from bootloader) 3. Compiled kernel using make kernel 4. then boot kernel using make boot Now when i run the test (MP_Dhry) i found that actually the results are not alligned i.e. there is no impact of disabling I-cache of CPU1 , infact the result is similar to the case when the I-cache of both(CPU0 and CPU1) cores are enabled. So to furthur debug this issue , i read SCTLR register (This is ARM core register which gives the state of I-cache) from following code: 1. For CPU0 : In file arch/arm/mach-sti/platsmp.c , Inside function sti_boot_secondary() : Read SCTLR register 2. For CPU1 :In file arch/arm/mach-sti/platsmp.c , Inside function sti_secondary_init() : Read SCTLR register And then recompiled and reboot kernel , Now the print shows that the CPU1 I-cache is actually DISABLED and CPU0 I-cache is enabled, Then why my result is not alligned. So i futhur applied print of SCTLR read inside sti_cpu_die() (In file arch/arm/mach-sti/platsmp.c): This function is called @ run time to shutdown CPU1 Now i again compiled kernel and reboot Linux , now this time also the kernel print shows that CPU1 I-cache is actually DISABLED and CPU0 I-cache is enabled. Now i used following command @run time after kernel boot: echo 0 > /sys/devices/system/cpu/cpu1/online (This command actually shutdown CPU1 which in turn call sti_cpu_die()) Now the print that i got is : CPU1 I-cache is actually ENABLED . So this explains why my result was not aligned with the expectation meaning even if i am disabling CPU1 I-cache , keeping CPU0 I-cache enabled , then also CPU1 I-cache is not getting DISABLED , meaning there is some other code which is actually enabling CPU1 I-cache. Now just to cross check i did same experiment with opposite configuartion i.e. i kept CPU1 I-cache Enabled and CPU0 I-cache Disabled . Now when i run test , my results are as if the I-cache of both cores are Disabled. The kernel prints @ boot time show that CPU0 I-cache is Disabled and CPU1 I-cache is Enabled (which is what is done from head.S file) But now the run time read of SCTLR register i.e. usnig command echo 0 > /sys/devices/system/cpu/cpu1/online (This command actually shutdown CPU1 which in turn call sti_cpu_die()) shows that CPU1 I-cache is Disabled . So from above experiment it seems that it is CPU0's configuartion which is ultimately applied to CPU1 too. So now my query is : Which piece of software is actually modifying the I-cache settings for CPU1 between sti_boot_secondary/ sti_scondary_init and sti_cpu_die ? Please help me to understand this mystery. Regards, Monika