Author: JT Smith
EE Times reports that “Aldec Inc., a longtime provider of
FPGA design tools, will make its first foray into the ASIC
market this week with Riviera, a Linux-based
mixed-language simulator. Riviera simulates VHDL, Verilog
and EDIF and comes with an HDL editor and source-level
debugger.”
FPGA design tools, will make its first foray into the ASIC
market this week with Riviera, a Linux-based
mixed-language simulator. Riviera simulates VHDL, Verilog
and EDIF and comes with an HDL editor and source-level
debugger.”
Category:
- Linux
