Author: JT Smith
Aldec Inc., a longtime provider of FPGA design tools,
will make its first foray into the ASIC market this week with Riviera, a
Linux-based mixed-language simulator. Riviera simulates VHDL, Verilog and
EDIF and comes with an HDL editor and source-level debugger, reports EEtimes. The simulation engine underlying Riviera is from Active-HDL, Aldec’s Windows
NT-based simulator. But Riviera is not a Linux port of Active-HDL, said Aldec
marketing vice president David Rinehart. “It’s native Linux. It’s the first step as we
move toward a Unix-based verification suite.”
will make its first foray into the ASIC market this week with Riviera, a
Linux-based mixed-language simulator. Riviera simulates VHDL, Verilog and
EDIF and comes with an HDL editor and source-level debugger, reports EEtimes. The simulation engine underlying Riviera is from Active-HDL, Aldec’s Windows
NT-based simulator. But Riviera is not a Linux port of Active-HDL, said Aldec
marketing vice president David Rinehart. “It’s native Linux. It’s the first step as we
move toward a Unix-based verification suite.”
Category:
- Linux
