Actel recently announced it has enhanced its Libero IDE to provide customers with faster timing closure when using the companys
flash-based ProASIC Plus FPGAs. With tighter integration between the Timer engine and timing-driven place and route, the Libero v5.2 IDE offers
push-button results that often meet or exceed customer requirements, thereby reducing the number of design iterations required to achieve timing
closure. Actels Libero v5.2 IDE, together with the enhanced Magma PALACE v1.1 physical synthesis software, enables designers using ProASIC Plus FPGAs
to achieve an average performance boost of 20 percent.
February 27, 2004