Author: JT Smith
Valiosys Inc., a French
formal-verification startup, has announced the availability
of TraLaLa, a transistor-level analysis and logic
abstraction tool that generates HDL descriptions from
transistor-level netlists, reports EETimes News. TraLaLa is available today on Sun and Linux platforms.
formal-verification startup, has announced the availability
of TraLaLa, a transistor-level analysis and logic
abstraction tool that generates HDL descriptions from
transistor-level netlists, reports EETimes News. TraLaLa is available today on Sun and Linux platforms.
