In this video, Andrew Siegel from Argonne National Laboratory presents: Trends in Next Generation HPC Architecture.
It is well known that the design of next generation HPC systems requires architectural choices that leave application developers in a largely unfamiliar parameter regime relative to the trends of the past twenty years — overall levels of concurrency, bandwidth to FLOP/s ratios, memory per floating point unit, use of instruction-level and shared-memory parallelism, power, and resilience characteristics are a few common examples. While constrained to some degree by the technology, in designing future HPC systems there is still considerable latitude both in specific design tradeoffs and the programming models that are used to optimally express them.
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